1. Field of the invention
The present invention relates to phase-locked circuits for preventing delay of clock signals distributed in integrated circuits and integrated circuit devices including the phase-locked circuits, and particularly to a phase-locked circuit for automatically adjusting the propagation delay time to avoid the difficulty in data transmission and reception in the synchronous digital data processing system and an integrated circuit device including the phase-locked circuit.
2. Description of the Background Art
Description will be made on the difficulty in data transmission and reception due to the propagation delay time in the digital data processing system. Especially, the propagation delay time occurring in the clock signals in the integrated circuits is a serious problem. One cycle of a clock signal is approximately 25 nS at 40 MHz. In integrated circuits, inputted external clock signals are generally distributed in the integrated circuits as internal clock signals after they have passed through an input buffer and a plurality of internal buffers connected in parallel. The plurality of stages of buffers are required because there is a limitation in the driving ability for the next stage of the buffers.
In this case, the external clock signal passes through the plural stages of buffers, so that the propagation delay time occurs between the internal clock signal and the external clock signal. For example, a delay of about 1-2 nS is caused when it passes through the input buffer. Now let us consider the case in which the data outputted from the first integrated circuit group in synchronization with the external clock signal is captured in synchronization with the external clock signal on the second integrated circuit.
FIG. 29 is a diagram showing a conventional integrated circuit. In the figure, 2 denotes an integrated circuit, 3 denotes a logic circuit provided in the integrated circuit 2, 4 denotes a sequential circuit provided in the logic circuit 3, 5 denotes a clock input terminal for receiving a clock signal CK1 inputted to the integrated circuit 2 from the outside, 6 denotes a data input terminal for receiving input data DI1 inputted to the integrated circuit 2 from the outside, 7 denotes a data output terminal for externally outputting the data processed in the integrated circuit 2, Bu1 denotes a buffer having its input end connected to the clock input terminal 5 to capture the clock signal CK1 inputted from the outside into the integrated circuit 2, Bu2 denotes a buffer having its input end connected to the data input terminal 6 to capture the input data DI1 inputted from the outside into the integrated circuit 2, Bu3 denotes a main buffer provided in the logic circuit 3 having its input end connected to an output end of the buffer Bu1 for supplying the clock signal to the sequential circuit 4, Bu4 through Bu6 denote buffers having their input ends connected to the output end of the buffer Bu3 and their output ends connected to the sequential circuit 4 for directly supplying the clock signal CK1 to the sequential circuit 4, 8 denotes a clock buffer including the buffers Bu3 through Bu6, and Bu7 denotes a buffer having its input end connected to the sequential circuit 4 and its output end connected to the data output terminal 7 for outputting the data DO1 processed in the sequential circuit 4 to the outside.
Now, a signal outputted from the buffer Bu1 is represented as SBu1, a signal outputted from the buffer Bu2 is represented as SBu2, a signal outputted from the buffer Bu4 is represented as SBu4, and a signal outputted from the sequential circuit 4 is represented as S4.
Next, the operation of the integrated circuit 2 shown in FIG. 29 will be described referring to FIG. 30. The input data DI1 is inputted from the data input terminal 6 in synchronization with the clock signal CK1 inputted to the clock input terminal 5. The input data DI1 includes a plurality of data such as DataA1, DataA2, and DataA3, which are sequentially inputted.
The inputted clock signal CK1 is captured into the integrated circuit 2 through the buffer Bu1. That is, the buffer Bu1 outputs the signal SBu1 into the integrated circuit 2. The signal SBu1 has a delay of a certain time .DELTA.t1 added in the buffer Bu1 with respect to the clock signal CK1. Furthermore, the clock buffer 8 receiving the signal SBu1 which is an output of the buffer Bu1 finally outputs the signal SBu4 and the like from the buffers Bu4 through Bu6 to the sequential circuit 4. For example, at this time, the signal SBu4 has a delay of a certain time .DELTA.t2 with respect to the signal SBu1. The delay time .DELTA.t2 is the signal delay in the buffer Bu3 and the buffer Bu4.
On the other hand, the inputted input data DI1 is captured into the integrated circuit 2 through the buffer Bu2. That is, the buffer Bu2 outputs the signal SBu2 into the integrated circuit 2. The signal SBu2 has a delay of a certain time added in the buffer Bu2 with respect to the clock signal CK1. Now, the first transitions of the clock signal CK1 for each clock are sequentially represented as CK1-.sub.1, Ck1-.sub.2, and CK1-.sub.3. The data DataA1 is captured in the sequential circuit 4 at the first transition (CKI-.sub.1) of the signal SBu4 corresponding to the first transition CK1-.sub.1 of the clock signal CK1 and processed.
Then, the data processed in the sequential circuit 4 is outputted to the buffer Bu7 as the signal S4 which is synchronous with the signal SBu4. The timing of outputting the signal S4 has a delay of a certain time .DELTA.t3 with respect to the signal SBu4. Due to the delay in the buffer Bu7, the output data DO1 outputted from the data output terminal 7 is further delayed by a certain time .DELTA.t4 with respect to the signal S4.
Next, the relations among each clock signal, input data and output data in the case where a plurality of above-described integrated circuits are connected will be described using FIG. 31. In FIG. 31, 1 denotes a clock oscillation circuit for outputting a signal CK, 2 denotes a circuit having a function equivalent to the integrated circuit 2 shown in FIG. 29, and 9 and 16 denote integrated circuits having sequential circuits. In FIG. 31, the same characters as those in FIG. 29 denote corresponding parts in FIG. 29, respectively.
In the figure, 11 and 18 denote sequential circuits provided in the integrated circuits 9 and 16, respectively, 12 and 19 denotes clock input terminals receiving clock signals CK2 and CK3 inputted into the integrated circuits 9 and 16 from the outside, respectively, 13 denotes a data input terminal receiving input data DI2 inputted into the integrated circuit 9 from the outside, 20 and 21 denote data input terminals receiving input data inputted into the integrated circuit 16 from the outside, 14 and 22 denote data output terminals for outputting data processed in the integrated circuits 9 and 16 to the outside, Bu8 and Bu15 denote buffers having input ends connected to the clock input terminals 12 and 19 to capture the clock signals CK2 and CK3 inputted from the outside into the integrated circuits 9 and 16, Bu9 denotes a buffer having its input end connected to the data input terminal 13 to capture the input data DI2 inputted from the outside into the integrated circuit 9, Bu16 and Bu17 denote buffers having input ends respectively connected to the data input terminals 20 and 21 to, capture the input data inputted from the outside into the integrated circuit 16, respectively, Bu 10 and Bu 18 denote main buffers respectively provided in the integrated circuits 9 and 16 having input ends connected to the output ends of the buffers Bu8 and Bu15 for supplying the clock signals respectively to the sequential circuits 11 and 18, Bu11 through Bu13 and Bu19 through Bu21 respectively denote buffers having input ends connected to the output terminals of the buffers Bu10 and Bu18 and output ends connected to the sequential circuits 11 and 18 for directly supplying the clock signals to the sequential circuits 11 and 18, 15 and 23 respectively denote clock buffers including the buffers Bu10 through Bu13 and the buffers Bu18 through Bu21, Bu14 denotes a buffer having its input end connected to the sequential circuit 11 and its output end connected to the data output terminal 14 to output the output data DO2 processed in the sequential circuit 11 to the outside from the integrated circuit 9, and 22 denotes a data output terminal having its input end connected to the sequential circuit 18 through a buffer for outputting output data DO3 processed in the sequential circuit 18 from the integrated circuit 16 to the outside.
A signal outputted from the buffer Bu8 is represented as SBu8, and a signal outputted from the buffer Bu11 is represented as SBu11. Also, signals outputted from the buffers Bu16 and Bu17 are respectively represented as SBu16 and SBu17, and a signal outputted from the buffer Bu19 is represented as SBu19.
Now, the integrated circuit 2 and the integrated circuit 9 form the first integrated circuit group. The integrated circuit 16 is the second integrated circuit. The integrated circuit 2 captures the input data DI1 from the data input terminal 6 in synchronization with the clock signal CK1 supplied to the clock input terminal 5 from the outside, processes the data in the sequential circuit 4, and outputs the output data DO1 produced in the sequential circuit 4 from the data output terminal 7 to the outside. The integrated circuit 9 captures the input data DI2 from the data input terminal 13 into the sequential circuit 11 in synchronization with the clock signal CK2 supplied to the clock input terminal 12 from the outside, processes the data in the sequential circuit 11, and outputs the output data DO2 produced in the sequential circuit 11 from the data output terminal 14 to the outside. The clock signals CK1 and CK2 differ from the clock signal CK outputted from the clock oscillation circuit 1 because the waveforms become dull and slight delays occur during the propagation, but they are treated as the same signals as the clock signal CK since the differences are very small.
The integrated circuit 16 has its data input terminal 21 connected to the data output terminal 7 of the integrated circuit 2 and its data input terminal 20 connected to the data output terminal 14 of the integrated circuit 9. The integrated circuit 16 receives the data DO1 and DO2 respectively processed in the integrated circuit 2 and the integrated circuit 9 as input data from the data input terminal 21 and the data input terminal 20, respectively. The inputted data DO1 and DO2 are inputted into the sequential circuit 18 as the signals SBu17 and SBu16 through the buffer Bu17 and the buffer Bu16, respectively. The sequential circuit 18 is driven by the signal SBu19 to process the inputted signals SBu16 and SBu17.
The operations of the integrated circuit 2, the integrated circuit 9 and the integrated circuit 16 described above are shown in FIG. 32. In the sequential circuit 4 of the integrated circuit 2, the input data DI1 including the data DataA11, dataA12 and DataA13 and the like which are inputted from the data input terminal 6 are processed in synchronization with the signal SBu4, and the output data DO1 including produced data DataB9, DataB10 and DataB11 and the like are outputted from the data output terminal 7 in synchronization with the signal SBu4. The signal SBu4 has a delay of a certain time .DELTA.t10 with respect to a first transition of the clock signal CK. The delay is caused in the buffer Bu1 and the clock buffer 8. The timings at which respective data of the output data DO1 are outputted delay with respect to the first transitions of the signal SBu4 due to processing in the sequential circuit 4 and passing through the buffer Bu7. Accordingly, the output data DO1 delays by a certain time .DELTA.t11 from the clock signal CK.
Similarly, in the sequential circuit 11 of the integrated circuit 9, the input data DI2 inputted from the data input terminal 13 is processed in synchronization with the signal SBu11 and the produced output data DO2 is outputted from the data output terminal 14 in synchronization with the signal SBu11. The timing at which the signal SBu11 is outputted has a delay of a certain time .DELTA.t12 with respect to the first transition of the clock signal CK. The delay occurs in the buffer Bu8 and the clock buffer 15. Being processed in the sequential circuit 11 and passing through the buffer Bu14, the output data DO2 is outputted from the integrated circuit 9 at the timing which is delayed from the first transition of the signal SBu11. Accordingly, the timing at which the output data DO2 is outputted is delayed by a certain time .DELTA.t13 with respect to the first transition of the clock signal CK.
The output data DO1 and the output data DO2 inputted to the data input terminals 20 and 21 of the integrated circuit 16 from the sequential circuits 4 and 11 are transmitted to the sequential circuit 18 through the buffer Bu17 and the buffer Bu16, so that they are further delayed by a certain time when arriving at the sequential circuit 18. The signal SBu16 inputted to the sequential circuit 18 from the sequential circuit 11 is added with the delay in the clock buffer 15, the sequential circuit 11 and the buffers Bu8, Bu14 and Bu16, and is delayed by a certain time .DELTA.t15 with respect to the first transition of the clock signal CK. Also the signal SBu17 inputted to the sequential circuit 18 from the sequential circuit 4 is added with the delay in the clock buffer 8, the sequential circuit 4 and the buffers Bu1, Bu7 and Bu17, and is therefore delayed by a certain time .DELTA.t14 with respect to the first transition of the clock signal CK. Now, since the delay times .DELTA.t15 and .DELTA.t14 of the signals SBu16 and SBu17 inputted to the sequential circuit 18 differ, the range in which the fluctuation in timing of the internal clock signal (the signal SBu19) for capturing and processing the signals SBu16 and SBu17 in the sequential circuit 18 can be permitted is narrowed to make the data transmission/reception difficult. Also, the processing speed of the integrated circuit 16 is slow because the data processings and the like are performed with the skew between the signals SBu16 and SBu17, which causes a trouble in speeding-up.
Especially, in the high speed data transfer in which the period of a external clock cycle is roughly equal to the level of the propagation delay times, there is a necessity of eliminating the propagation delay time between the internal clock signal and the external clock signal to eliminate difference in phase as the first measure to precisely transfer and receive data.
As an example, there is the clock distributing circuit disclosed in Japanese Patent Laying-Open No. 62-261216. This example has a phase-locked circuit including a delay circuit having external clock signals as input and having a plurality of delay elements connected in series, a selection circuit for sequentially selecting respective tap outputs of the delay circuit corresponding to output of a counter, a buffer circuit for distributing clock signals selected by the selection circuit, and a control circuit for counting up a value of the counter if there is a phase difference between the buffer circuit output and the external clock signal.
In the integrated circuit having the phase-locked circuit provided therein, the value counted by the counter increases until the phase of the buffer circuit output, i.e., the internal clock signal agrees with the external clock signal, where the phase of the internal clock signal is delayed, and the counting operation is stopped when the external clock and the internal clock agree in phase to determine the phase of the internal clock signal.
The structure has some weak points, such as, the operation speed of the counter is slow, such a circuit for coding the counter output and selecting the outputs from the taps is required, so that it is not suitable for speeding up and miniaturizing of the circuits.
Furthermore, in the integrated circuit using the clock distribution circuit disclosed in Japanese Patent Laying-Open. No. 62-26126, the difference in phase of the external clock signal and the internal clock signal is made small so that the propagation delay time caused in the clock buffer can be neglected for precise data transmission and reception, but the propagation delay time in the sequential circuit, the output buffer and the like added to the output data can not be removed in this case, either.
In the conventional integrated circuit devices having such structures as described above, there has been a problem that the time required for the phase-locked circuit provided in the integrated circuit to determine the phase of the internal clock is long, so that it has been difficult to transmit and receive data with integrated circuits performing high-speed data processings being connected to each other.
Also, The output timing of the data outputted from the integrated circuits 2, 9, 16 has a considerably large delay time from a first transition of the clock signal CK supplied to the integrated circuits 2, 9, 16, and the skews differ in respective integrated circuits 2 and 9. Accordingly, there have been problems that the data transmission and receipt are difficult and the processing speed of the integrated circuit 16 which receives and processes the data is slow not to enable high speed data processings.